1. Technical Field
The present invention relates to the technical field of integrated circuits (ICs), and more particularly, to an IC having a scan chain and a testing method for a chip.
2. Description of Related Art
A method commonly used to test a digital logic section of a chip comprised of large-scale integrated circuits (LSICs) is the scan chain test. A scan chain consists of scan registers. A general structure of a non-scan register is as shown in FIG. 1A. At a rising edge of a clock signal (clk), a data value from a data input terminal (d) is obtained at a data output terminal (q) of the register and is kept unchanged until the next rising edge of the clock signal. Then, the data value is updated into a new data value of the data input terminal (d). A general structure of a scan register is as shown in FIG. 1B. In contrast to the non-scan register, the scan register additionally comprises a data input selector at the data input terminal. In a scan disabled status (i.e., scan_enable=0), the data input d′ of the register is d. In a scan enabled status (i.e., scan_enable=1), the data input d′ of the register becomes the scan data input scan_in; and at a rising edge of the clock signal (clk), the data value obtained at the output terminal (q/scan_out) of the register may be either d or scan_in depending on the value of the scan enable signal (scan_enable). By connecting the data output terminal q/scan_out of each scan register with the scan data input terminal scan_in of a next scan register in sequence, a long register bar can be formed, which is called a scan chain. FIG. 1C is an original design sketch before the scan chain is inserted, and FIG. 1D is a full-scan design sketch after the scan chain is inserted.
The registers in the scan chain feature scan controllability and scan observability. By controlling a clock signal and a scan enable signal connected to each of the scan registers and the first scan input signal (scan_in) connected to a chip pin, the Automatic Test Program Generation (ATPG) tool can control the value of the data output terminal of any of the scan registers in the whole scan chain; alternatively, the value of the data output terminal of any of the scan registers in the whole scan chain may be obtained according to the last scan output signal (scan_out) connected to a chip pin. Thus, in the scan enabled status (i.e., scan_enable=1), an initial value is set for the scan register; and when the scan chain is switched to the scan disabled status (i.e., scan_enable=0) (i.e., switched to the normal functional circuit of the digital circuit), the clock signal (clk) is allowed to experience a transition once so that the logic data input (d) in the functional circuit is latched to the output terminal (q/scan_out) of the register. Then, the register is switched back into the scan enabled status (scan_enable=1) to output the value latched in the register through shifting. By comparing the value with a known value that is ought to be obtained, it can be known whether the circuit has a defect caused in the manufacturing process.
Generally, in order to cater for different needs in the market, integrated circuits (ICs) might be packaged in forms of various types of packages. Then, in order to ensure that the scan chain test can be carried out on all types of packages, input/output (I/O) interfaces that are always packaged as external pins in each package type (i.e., an intersection set of I/O interfaces that are packaged as external pins in each package type) must be found and external pins corresponding to the intersection set are used as usable pins of the scan chain. Referring to FIGS. 2A, 2B and 2C, three different package types of a same chip are shown therein respectively. As can be seen, only I/O interfaces io1, io2, io6, io7 are always packaged as external pins in each of the three package types. Then, in order to ensure that the scan chain test can be carried out on the chip of each of the package types, generally only external pins pin1, pin2, pin4, and pin5 corresponding to the I/O interfaces io1, io2, io6 and io7 after being packaged are used as usable pins of the scan chain. The structure of the scan chain is shown in FIG. 2D.
This method is feasible for packages whose functions are highly overlapped with each other. However, for packages whose functions vary greatly from each other, the number of I/O interfaces that can always be packaged as external pins in each type of package is very small; and correspondingly, the number of scan chains that can be inserted becomes very small, and in case of a large-scale design, the number of registers in each scan chain will be very large. Because of the fact that the larger the number of registers in a single scan chain is, the longer the testing time and the higher the testing cost will be, this method tends to considerably increase the testing cost and the testing time.